Abstract of the project

 

One of the most critical challenges of the ITRS overall design technology (2010) is fault-tolerant computation. The increase in integration density and the requirement of low-energy consumption can only be sustained through low-powered components, with the drawback of a looser robustness against transient errors. In the near future, electronic gates to process information will be inherently unreliable.

In this project, we want to address this problem with a bottom-up approach, starting from an existing application (a GPS receiver) and adding some redundant mechanisms to allow the GPS receiver to be tolerant to transient errors due to low voltage supply.

Our objective is to produce an ASIC with two versions of the application: a standard GPS receiver and a hardened GPS receiver (a simple L1 band GPS receiver). Our ambition is to decrease by a factor of 4 the energy of the hardened GPS receiver thanks to a very low power supply voltage while keeping an acceptable degradation of the quality of service provided by the device (i.e. mean duration from a "cold start' to a position, precision of the measure)

To interpret this in terms of world energy savings, we assume on the order of 10 billion GPS receiver units in the world in the near future (a conservative hypothesis), each working 1% of the time. Each mW saved with fault tolerant design will give a global saving of 10^-6 (1 mW express in KW) x 10^10 (number of GPS) X 10^-2 (rate of utilisation) x 24  x 356 (number of hours in a year) =  0.88 x 10^6 KW.h per year in the world. Note also that GPS are mainly used in application that implies mobility. Mobile devices don't have direct access to powerline energy and should use batteries and/or produce directly its own electrical energy (energy harvesting devices). In both cases, the cost and the enviromental impact to provide energy is high.

During this project, we will develop knowledge at several levels: the effect of low voltage at transistor level, application of robust non-conventional arithmetic, the downstream impact of gate level errors on arithmetic and functional operation, refinement of high level specification (reliability and quality of service) to low level arithmetic and functional requirements. Measurement of the ASIC product will allow us to test the proposed methods on a real design case and provide very useful feedback.

The RELIASIC project will trigger a scientific community in the area of fault-tolerant computation for very low power processing with the focus ``Energy and resource efficiency in ICT'' of the Labex CominLab. As a longer research perspective, the consortium wants to capitalize on this project by extending the knowledge obtained with the RELIASIC bottom-up approach to define new computation methods, new design methodology and tools for fault-tolerant computation.